Domain-specific Optimization of Reconfigurable Array Architecture

With the increasing requirements of more flexibility and higher performance in embedded systems design, the concept of reconfigurable computing has become more attractive. Especially, there have been many coarse-grained reconfigurable array architectures proposed and/or commercialized. However, the existing reconfigurable array architectures have been designed without the concept of application-specific optimization, resulting in inefficient usage of area and power. Functional resources that take large area can be shared among multiple processing elements and those with long delay can be pipelined. Thus the hardware cost can be effectively reduced without any performance degradation for some application domains. In this paper, we propose a reconfigurable array architecture template for domain-specific optimization. We also present several case studies including H.263 and 3D graphics design. The case studies show that our approach is much more efficient in both performance and area compared to existing reconfigurable architectures.